Search found 109 matches
- 23 Apr 2021, 16:19
- Forum: EZ-BIST
- Topic: Halt at ICG while auto clock tracing
- Replies: 0
- Views: 43671
Halt at ICG while auto clock tracing
[Question] While executing auto clock tracing in EZ-BIST, it will be halted if trace to ICG. [Answer] While executing auto clock tracing, designer has to define ICG information in BFL file like following figure. https://forum.istart-tek.com/ext/dmzx/fileupload/file-files/51/f57f018/d288bd5/dce67b8b...
- 23 Apr 2021, 16:16
- Forum: EZ-BIST
- Topic: Formality checking
- Replies: 0
- Views: 43587
Formality checking
[Question] If designer wants to do formality checking to compare the functionality of design with/without MBIST, how to do it?
[Answer] To do formality checking with or without MBIST, designer just needs to tie TDI signal to 0. In this condition, MBIST function will not execute.
[Answer] To do formality checking with or without MBIST, designer just needs to tie TDI signal to 0. In this condition, MBIST function will not execute.
- 23 Apr 2021, 16:10
- Forum: EZ-BIST
- Topic: How to get diagnosis data & analysis?
- Replies: 0
- Views: 43681
How to get diagnosis data & analysis?
[Question] How to get diagnosis data and analysis? [Answer] If designer enable diagnosis function. EZ-BIST diagnosis data will generate and output from TDO port to ATE equipment. Testing engineer can collect TDO data after capture_DIAG_DR and then analysis the output data. https://forum.istart-tek....
- 23 Apr 2021, 15:49
- Forum: EZ-BIST
- Topic: Do MBIST and normal function use the same data path?
- Replies: 0
- Views: 44481
Do MBIST and normal function use the same data path?
[Question] After inserting iSTART MBIST into IC, whether MBIST and normal function use the same data path? [Answer] If memory without test port, after inserting MBIST into memory, it will add one more MUX in front of memory. This MUX can switch the data path between MBIST or normal function. So, wh...
- 23 Apr 2021, 15:45
- Forum: EZ-BIST
- Topic: How to execute BIST testing?
- Replies: 0
- Views: 43708
How to execute BIST testing?
[Question] How does EZ-BIST execute memory testing? Are one by one controller or all controllers execute memory testing together? [Answer] Through SDI testing command, testing engineer can specify individual controller to do memory testing. Or can specify all controllers to do memory testing. Actua...
- 23 Apr 2021, 14:13
- Forum: NVM
- Topic: NVM trimming implementation
- Replies: 0
- Views: 46963
NVM trimming implementation
[Question] In your NVM solution, how does iSTART fulfill testing analog trimming voltage function? [Answer] About adjust NVM analog trimming voltage, through tool’s interface, testing engineer can use specified testing command to adjust the register of trimming data till meet expected analog voltag...
- 23 Apr 2021, 14:08
- Forum: START
- Topic: How to reorganize memory grouping?
- Replies: 0
- Views: 23231
How to reorganize memory grouping?
According to design requirements, for example, testing power supply, memory location …etc., customers need particular memory grouping to meet their design requirements. In START tool, designers can arrange memory grouping through reorganizing meminfo file. The following shows the meminfo data forma...
- 23 Apr 2021, 14:03
- Forum: START
- Topic: Area comparison in several BIST conditions
- Replies: 0
- Views: 23173
Area comparison in several BIST conditions
Following comparisons show the MBIST’s area in different conditions. Following table only show area of MBIST and MBISR and enable full function diagnosis only. Therefore, the area’s increasing rate is higher than expectation. https://forum.istart-tek.com/ext/dmzx/fileupload/file-files/51/6f50344/40...
- 23 Apr 2021, 13:52
- Forum: NVM
- Topic: NVM Testing Platform features
- Replies: 0
- Views: 21418
NVM Testing Platform features
iSTART supports MTP test platform. Following show the platform features: Clock Assumption - System: 16.6MHz - JTAG: 10MHz Support configurable to 8kx16 MTP size IEEE1149.7 interface - ICG (Integrated Clock Gating) cell are used to generate tck in IEEE1149.7 wrapper. Before synthesis, li...
- 21 Apr 2021, 08:34
- Forum: EZ-BIST
- Topic: SDC file cannot be recognized
- Replies: 0
- Views: 21326
SDC file cannot be recognized
[Question] In BFL flow, if BFL does not define clock domain, SDC file could not be recognized by EZ-BIST tool and no error report.
[Answer] To use SDC file in BFL stage, auto clock trace should turn on in BFL file. Please confirm if clock trace turns on.
[Answer] To use SDC file in BFL stage, auto clock trace should turn on in BFL file. Please confirm if clock trace turns on.