Search found 109 matches

by iSTART
28 May 2021, 16:05
Forum: Webinar
Topic: 漫談芯測生態系統
Replies: 0
Views: 4379

漫談芯測生態系統

by iSTART
24 Apr 2021, 10:17
Forum: EZ-BIST
Topic: How to generate meminfo file
Replies: 0
Views: 4401

How to generate meminfo file

[Question] If I want to assign meminfo file to BFL’s memory_list, how can I generate this meminfo file? [Answer] After designer executing BFL flow, a meminfo file will be generated under work path (default is \mbist) and named [project].meminfo. Designer can adjust grouping in the meminfo according...
by iSTART
24 Apr 2021, 10:16
Forum: EZ-BIST
Topic: Integrator_mode enable
Replies: 0
Views: 4384

Integrator_mode enable

[Question] If I want to run BII flow, should I turn on “integrator_mode” in BFL file? [Answer] Yes, if user want to execute BII flow to integrate all controller, user should turn on “integrator_mode”. In BII flow, EZ-BIST tool will integrate all controller pins into a single INTEG module. And then ...
by iSTART
24 Apr 2021, 10:12
Forum: EZ-BIST
Topic: Specify MUX cell library
Replies: 0
Views: 3825

Specify MUX cell library

[Question] How can I specify our own MUX cell to replace EZ-BIST tool MUX? [Answer] Designer can use following steps to replace EZ-BIST tool MUX. 1. In BFL, specify user’s MUX library information file as following. https://forum.istart-tek.com/ext/dmzx/fileupload/file-files/51/ee129a6/a8baf5d/11866...
by iSTART
24 Apr 2021, 10:03
Forum: EZ-BIST
Topic: Different memory types group under a sequencer
Replies: 0
Views: 3856

Different memory types group under a sequencer

[Question] We use meminfo file as memory grouping template for EZ-BIST tool. But while we arrange single port and 2 port these 2 memory types under a sequencer, it has problem. Why? [Answer] Under a sequencer, only allows to put a kind of memory type. Designer cannot assign different types of memor...
by iSTART
24 Apr 2021, 09:28
Forum: EZ-BIST
Topic: Algorithm suggestion
Replies: 0
Views: 3843

Algorithm suggestion

[Question] Does iSTART support following algorithms? Scan -> ? March d2PF -> ? March s2PF -> ? [Answer] 1) Scan is used for detecting SAF (Stuck-At Fault), in general, more complex testing algorithms can cover this defect. For example, March C-, dualMarch 19N …etc, these algorithms can detect all d...
by iSTART
24 Apr 2021, 09:20
Forum: EZ-BIST
Topic: Q_pipeline
Replies: 0
Views: 3857

Q_pipeline

[Question] While we run synthesis, because we specify MBIST clock to use function clock, then SRAM’s output will pass through MBIST combinational logic, it causes the timing of SRAM output tighter. And it has timing violation problem. As we know, it can add a pipeline to fix this timing issue. Do S...
by iSTART
24 Apr 2021, 09:06
Forum: EZ-BIST
Topic: Bottom-up flow
Replies: 0
Views: 3826

Bottom-up flow

To construct a large integrated circuit, designers can adopt bottom-up flow, one by one blocks, to accomplish MBIST design. EZ-BIST tool provides an easy way to assist user adding MBIST into such large integrated circuit architecture. https://forum.istart-tek.com/ext/dmzx/fileupload/file-files/51/6...
by iSTART
23 Apr 2021, 16:24
Forum: EZ-BIST
Topic: Parallel testing
Replies: 0
Views: 3814

Parallel testing

[Question] In BFL setting, what are the difference while PRL_ON = 1 / 0 [Answer] In TB file (test bench), https://forum.istart-tek.com/ext/dmzx/fileupload/file-files/51/4c21979/0f53ffb/45b15b96e202eab74f406f02b5ce2554.png If PRL_ON = 0, the testing will be one by one memories group under a controll...
by iSTART
23 Apr 2021, 16:20
Forum: EZ-BIST
Topic: Integrate 2 memories case, can share one TPG in this case?
Replies: 0
Views: 3796

Integrate 2 memories case, can share one TPG in this case?

[Question] To avoid routing congestion problem, we will combine two memories, for example 8K + 8K, and treat as one 16K memory. In such case, can these two memories share one TPG. [Answer] For this case, user can use UDM (user define memory) file to define this combined memory. In BFL file, these t...