Search found 109 matches

by iSTART
21 Apr 2021, 08:32
Forum: EZ-BIST
Topic: Define retention time
Replies: 0
Views: 1955

Define retention time

In some EZ-BIST’s memory testing algorithms, they allow memories to do retention testing. For example, March-RET algorithm is <(wb) (SLP) <(rb) >(wa) (SLP) >(ra) Where (SLP) indicates sleep time and unit is 1T. If want to extend the SLP time more than 1T, designer can specify the retention time to ...
by iSTART
21 Apr 2021, 08:31
Forum: EZ-BIST
Topic: Skip wrap memory
Replies: 0
Views: 1968

Skip wrap memory

In some applications, designer will wrap several memories. And this wrap will be treated as a bigger memory. In BFL flow, for avoiding identifying the wrap as memory, designer can use parameter “skip_wrap_mem” to ignore this wrap module. And these wrap module will not list in the generated *.meminf...
by iSTART
21 Apr 2021, 08:29
Forum: EZ-BIST
Topic: How to add System Verilog file into BFL filelist
Replies: 0
Views: 1949

How to add System Verilog file into BFL filelist

[Question] In memory models, if they are System Verilog files, how can I add such files into START tool. [Answer] If memory is System Verilog file, in filelist, designer can add option “-sv” in front of memory models. Following example, test.v is System Verilof file, so we add “-sv” in front of “./...
by iSTART
21 Apr 2021, 08:26
Forum: EZ-BIST
Topic: How to get BFL template file
Replies: 0
Views: 1945

How to get BFL template file

[Question] How to generate BFL & BII template files? [Answer] To get BFL & BII template files, user can refer to following steps. 1. Execute “ezbist --tempgen” instruction. 2. In the template generator menu, Enter “ 1 ”, it will generate BFL template file 3. In the template generator menu, ...
by iSTART
21 Apr 2021, 08:19
Forum: START
Topic: How to execute memory testing
Replies: 0
Views: 1953

How to execute memory testing

[Question] How START’s design executes memory testing? All controller’s memories test together or one by one controller to do memory testing? About circuit design, do they have any different between parallel testing or serial testing? [Answer] Testing engineer can assign all controller’s memories o...
by iSTART
19 Apr 2021, 08:50
Forum: START
Topic: Does MBIST support multi-chain design?
Replies: 0
Views: 1925

Does MBIST support multi-chain design?

[Question] Currently, in iSTART multi chain, it supports repair controller only. In the feature, do you extend this function to BIST controller? That means if MBIST controller power off, other MBIST controller still can work normally. [Answer] BIST controller does not need to support multi chain ar...
by iSTART
19 Apr 2021, 08:49
Forum: START
Topic: SRAM repair how to execute repair function
Replies: 0
Views: 1932

SRAM repair how to execute repair function

[Question] SRAM repair how to execute repair function? Does JTAG control MBIST and repair function? [Answer] Repair function is not controlled by JTAG. In iSTART design, if MBIST executes memory testing and found defects, MBISR will automatically execute repair function to do memory repairing, and ...
by iSTART
19 Apr 2021, 08:47
Forum: START
Topic: JTAG interface
Replies: 0
Views: 1954

JTAG interface

Following picture shows JTAG 1149.1 wrapper design and pins definitions

Image
by iSTART
19 Apr 2021, 08:45
Forum: START
Topic: Force value in test bench
Replies: 0
Views: 1947

Force value in test bench

[Question] We cannot see any logic design to control the test pattern in the “force” syntax, do we need adding design to modify these force codes by ourselves? [Answer] Because some customers use the testcase provided by START but don’t correctly assign initial data to don’t touch ports. And it cau...
by iSTART
19 Apr 2021, 08:43
Forum: START
Topic: Gate cell insertion
Replies: 0
Views: 1917

Gate cell insertion

START tool provides a methodology to let user automatically insert gate cell in memory clock: 1. Specify gate cell library in BII file. User also can add MUX in front of gate cell if necessary. The gate cell library format will describe in step 3. And MUX cell library format will describe in step 4...