[Question] In memory models, if they are System Verilog files, how can I add such files into START tool.
[Answer] If memory is System Verilog file, in filelist, designer can add option “-sv” in front of memory models. Following example, test.v is System Verilof file, so we add “-sv” in front of “./memory/test.v” to inform START tool that test.v is a System Verilog file.
EZ-BIST tool usage, BFL flow, BII flow, memory grouping
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