How to add System Verilog file into BFL filelist

EZ-BIST tool usage, BFL flow, BII flow, memory grouping
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iSTART
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Joined: 08 Dec 2020, 15:53

How to add System Verilog file into BFL filelist

Post by iSTART »

[Question] In memory models, if they are System Verilog files, how can I add such files into START tool.

[Answer] If memory is System Verilog file, in filelist, designer can add option “-sv” in front of memory models. Following example, test.v is System Verilof file, so we add “-sv” in front of “./memory/test.v” to inform START tool that test.v is a System Verilog file.


// run.f
-v ./memory/rf_2p_24x28.v
-v ./memory/sram_sp_4096x64.v
-v ./memory/rf_sp_128x22.v
-v ./memory/sram_dp_1024x64.v
-v ./memory/rf_2p_24x56.v
-v ./memory/sram_sp_2048x64.v
-v ./memory/sram_sp_640x32.v
-v ./memory/rf_2p_64x64.v
-v ./memory/rf_2p_72x14.v
-sv ./memory/test.v

./top.v
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