[Question] While we run synthesis, because we specify MBIST clock to use function clock, then SRAM’s output will pass through MBIST combinational logic, it causes the timing of SRAM output tighter. And it has timing violation problem.
As we know, it can add a pipeline to fix this timing issue. Do START tool have such function to add a pipeline?
In EZ-BIST BFL setting, user can use following setting to add pipeline.
Set Q_pipeline = yes.
EZ-BIST tool usage, BFL flow, BII flow, memory grouping
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