Bottom-up flow

START tool usage, BFL flow, BII flow, memory grouping, advanced application
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iSTART
Posts: 348
Joined: 08 Dec 2020, 15:53

Bottom-up flow

Post by iSTART »

To construct a large integrated circuit, designs can adopt bottom-up flow to accomplish MBIST design one by one blocks. START tool provides an easy way to assist user adding MBIST into such large integrated circuit architecture.
Figure1.png
Figure1.png (101.01 KiB) Viewed 2008 times
Figure1.png
Figure1.png (101.01 KiB) Viewed 2008 times
Figure 1: An Example for bottom-up architecture

In Figure 1, there are 3 modules, design1, design2 and design 4 need to be hardened. In this case, it has to execute twice bottom-up flows. In addition, the BIST circuit in design 3 module need to be inserted while executing design 1 BFL flow.

To utilize START to execute bottom-up flow, user should push the inserted BIST circuit to top module. For example, in Figure 1, user should insert BIST circuit into design 2 and design 4.

Then, user insert BIST circuit into the design 1 module. Meanwhile, BIST also needs to be inserted into designed 3. And then insert the BIST circuit into the top level of chip_top. Finally, integrated all BIST circuits and use a standard JTAG interface as the unique control interface.

Since design 2 and design 4 modules are in the lowest level, the settings of these 2 modules should define following 2 assignments.
set bist_interface = ieee1500
set integrator_mode = no


Integrator_mode assign to “no”, START will generate *.blockinfo text file.

In the design 1 module, one more option “block_path” should be added. The settings as below:
 set bist_interface = ieee1500
 set integrator_mode = no
 set block_path = ./mbist_design2/START_design2.blockinfo | ./mbist_design4/START_ design4.blockinfo


After design 1 module settings done, user could insert design 2 and design 4 with BIST into design1.f. Please refer to Figure 2.

Figure2.png
Figure2.png (349.08 KiB) Viewed 2008 times
Figure2.png
Figure2.png (349.08 KiB) Viewed 2008 times
Figure 2: An Example to insert design 2 & 4 into design 1

To insert BIST into TOP module, it is similar to design 1, except integrator_mode should assign to yes. The assignments of other options are the same as the previous steps. Please notice the following assignments:

 set bist_interface = ieee1500
 set integrator_mode = yes
 set block_path = ./mbist_design1/START_design1.blockinfo


The file-list of design 1 with BIST put into chip_top.f as figure 3:

Figure3.png
Figure3.png (157.05 KiB) Viewed 2008 times
Figure3.png
Figure3.png (157.05 KiB) Viewed 2008 times
Figure 3: Insert design 1 module to chip top

User can integrate all BIST circuits through START integration flow. And it should be assigned *.postfixinfo file as below. START will insert BIST circuit into chip_top and then generate *.postfixinfo file.

set postfixinfo = ./mbist_chip_top/START_chip_top.postfixinfo

Figure 6-7 shows the architecture after executing these integration flow in this chapter.

Figure6-7.png
Figure6-7.png (242.31 KiB) Viewed 2008 times
Figure6-7.png
Figure6-7.png (242.31 KiB) Viewed 2008 times
Figure 6-7 Bottom-up flow complete architecture
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