Q_pipeline

START tool usage, BFL flow, BII flow, memory grouping, advanced application
Post Reply
iSTART
Posts: 348
Joined: 08 Dec 2020, 15:53

Q_pipeline

Post by iSTART »

[Question] While we run synthesis, because we assign MBIST clock using function clock, then SRAM’s output will pass through MBIST combinational logic, it causes the timing of SRAM output tighter. And it has timing violation problem.
As we know, it can add a pine to fix this time issue. Do START tool have a function to add a pipeline?

[Answer]
In START BFL setting, user can use following setting:
Set Q_pipeline = yes.
Post Reply