[Question] While we run synthesis, because we assign MBIST clock using function clock, then SRAM’s output will pass through MBIST combinational logic, it causes the timing of SRAM output tighter. And it has timing violation problem.
As we know, it can add a pine to fix this time issue. Do START tool have a function to add a pipeline?
In START BFL setting, user can use following setting:
Set Q_pipeline = yes.
START tool usage, BFL flow, BII flow, memory grouping, advanced application
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