[Answer] Following picture is an example of customer’s system block diagram.
After inserting iSTART MBIST & MBISR, the block diagram will become following picture, the blue blocks represent iSTART inserted MBIST & MBISR modules. They include controller (CTR_#), sequencer (SEQ_N), test pattern generate (TPG_#) and TRA (TRA_#)
- MBISR insert one multiplexer in front of each memory if memory without supporting test port, and this multiplexer lightly affects the function timing.
- The blue blocks represent MBISR circuits, the other blocks stand for customer’s represent customer design.
- Users can plan the number of CTR and SEQ as well as place them in any position arbitrarily.
- One memory corresponds to one TPG, TCR and TRA. TRA only generated when the memory support redundancy memory for repairing.
- SRAM_2 represents supporting test port. So, START tool will not insert a MUX in front of memory.
- If user has time violation issue, user can try following solution to fix:
1. Adjust CTR and SEQ position
2. Increase CTR and SEQ amount to shorten the distance among CTR, SEQ and memories
3. Improve users their own design.
4. Change standard library.
5. Change memory model.