- Using GUI interface in tool platform, directly generate corresponding BIST/BISR IP for various NVM size.
- Simplified platform, good reusability, greatly reducing NVM BIST design time.
- Test bench directly generates the corresponding ATE test vector STIL/Text format
- Support NVM scramble test design.
- The generated BIST design is soft IP, easily integrate into SoC design.
3. Diagnosis function
- According to customer feedback, compare to original solution, the test time could be reduced to 1/5, significantly reducing test cost.