- Clock Assumption
- System: 16.6MHz
- JTAG: 10MHz
- Support configurable to 8kx16 MTP size
- IEEE1149.7 interface
- ICG (Integrated Clock Gating) cell are used to generate tck in IEEE1149.7 wrapper. Before synthesis, library cell can be replaced to user’s
- IR Mode
- BYPASS mode
- Set related test conditions
- test results capture
- Timing parameters can be adjusted
- WS1 , WS2, FT test item can be enable and disable
- Provide user mode for the user to operate on MTP in test mode
- MTP data output capture
- Provide diagnosis mode
- Implement all MTP vendor’s recommendations test items
- Include CP1, CP2, FT steps
Following pictures shows the architecture of MTP test platform.
