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MBIST Area Statistic

Posted: 20 Jan 2021, 09:20
by iSTART
In this section, it lists referenced area statistics while adding MBIST into design.

Design architecture:
Memory: Single-port SRAM *20 and ROM *1
Process: TSMC 55nm
Library: sc9_cln55lp_base_rvt_ss_typical_max_1p08v_125c
NAND Gate area:1.44 um2


Default BFL settings: (default.bfl)
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P1.png (84.91 KiB) Viewed 5350 times
P1.png
P1.png (84.91 KiB) Viewed 5350 times

Synthetic area of default.bfl (Unit:um2): Following area information are based on default.bfl.
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P2.png
P2.png (149.72 KiB) Viewed 5350 times

Following table show the area rate variation while setting change.
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P3.png (47.96 KiB) Viewed 5350 times
P3.png
P3.png (47.96 KiB) Viewed 5350 times

Following table shows the area rate variation while selecting different interface.
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P4.png
P4.png (51.25 KiB) Viewed 5350 times

Following table shows the area rate variation while using different algorithm and algorithm_selection setting.
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P5.png
P5.png (34.2 KiB) Viewed 5350 times

Following table shows the area rate variation while selecting different background testing pattern and its data inverse setting.
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P6.png (60.78 KiB) Viewed 5350 times
P6.png
P6.png (60.78 KiB) Viewed 5350 times

Following table shows the area rate variation in several different bypass settings.
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P7.png
P7.png (56.03 KiB) Viewed 5350 times

Diagnosis can assist user to analysis the memory errors. Following table shows the area rate variation in several different diagnosis settings.
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P8.png
P8.png (54.12 KiB) Viewed 5350 times

In default BFL setting, it includes one controller, two sequencers and two groups. Following table shows the rate variation while grouping setting change.
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P9.png (53.25 KiB) Viewed 5350 times
P9.png
P9.png (53.25 KiB) Viewed 5350 times