Design architecture:
Memory: Single-port SRAM *20 and ROM *1
Process: TSMC 55nm
Library: sc9_cln55lp_base_rvt_ss_typical_max_1p08v_125c
NAND Gate area:1.44 um2
Default BFL settings: (default.bfl)
- P1.png (84.91 KiB) Viewed 5349 times
- P1.png (84.91 KiB) Viewed 5349 times
Synthetic area of default.bfl (Unit:um2): Following area information are based on default.bfl.
- P2.png (149.72 KiB) Viewed 5349 times
- P2.png (149.72 KiB) Viewed 5349 times
Following table show the area rate variation while setting change.
- P3.png (47.96 KiB) Viewed 5349 times
- P3.png (47.96 KiB) Viewed 5349 times
Following table shows the area rate variation while selecting different interface.
- P4.png (51.25 KiB) Viewed 5349 times
- P4.png (51.25 KiB) Viewed 5349 times
Following table shows the area rate variation while using different algorithm and algorithm_selection setting.
- P5.png (34.2 KiB) Viewed 5349 times
- P5.png (34.2 KiB) Viewed 5349 times
Following table shows the area rate variation while selecting different background testing pattern and its data inverse setting.
- P6.png (60.78 KiB) Viewed 5349 times
- P6.png (60.78 KiB) Viewed 5349 times
Following table shows the area rate variation in several different bypass settings.
- P7.png (56.03 KiB) Viewed 5349 times
- P7.png (56.03 KiB) Viewed 5349 times
Diagnosis can assist user to analysis the memory errors. Following table shows the area rate variation in several different diagnosis settings.
- P8.png (54.12 KiB) Viewed 5349 times
- P8.png (54.12 KiB) Viewed 5349 times
In default BFL setting, it includes one controller, two sequencers and two groups. Following table shows the rate variation while grouping setting change.
- P9.png (53.25 KiB) Viewed 5349 times
- P9.png (53.25 KiB) Viewed 5349 times