Dynamic Memory Testing implemention

[iSTART]

DMT (Dynamic Memory Testing) is a unique implementation among memory testing and developed for some electronic devices, such as secure devices, server system, uninterruptible power equipment …etc. These applications may run a very long time after system power-on. To guarantee these systems work properly during system running, they should have a mechanism to verify system themselves while system on leisure time.
iSTART’s DMT is a powerful feature. It can build-in and integrate with customer’s IC (Integrated Circuit). DMT assists system to do self-testing when the system not busy status. iSTART DMT function can implement on SRAM, eFlash, ROM …etc. After testing finished, if DMT detect some defects in memory, it can run repair flow to recover the failed memory cell and make system still work properly.

Block Diagram
Figure 1 shows DMT block diagram. It includes two major blocks, APB CTR and MBIST/MBISR. APB CTR controls all APB signals. If APB CTR got memory BIST and repair command from host. It will enable MBIST/MBISR starting memory testing and repairing.

Figure 1: DMT architecture

DMT architecture.jpg (49.38 KiB) Viewed 5726 times

DMT architecture.jpg (49.38 KiB) Viewed 5726 times

BUS Interface Signals

Table 1 lists APB interface signals. And table 2 lists the signals which info the results of MBIST & MBISR.

Table 1 APB Interface Signals.jpg (77.23 KiB) Viewed 5726 times

Table 1 APB Interface Signals.jpg (77.23 KiB) Viewed 5726 times

Table 1 APB Interface Signals

Table 2 System Interrupt Signals.jpg (53.09 KiB) Viewed 5726 times

Table 2 System Interrupt Signals.jpg (53.09 KiB) Viewed 5726 times

Table 2 System Interrupt Signals

DMT Registers

There are 4 types of DMT registers, ADDR, DATA, CTRL and STATUS.

Terminlolgy:
• IM: Implementation dependent/determined
• RO: Read Only register/field by software. Any software write to RO register/field will be silently ignored by Hardware
• RW: Read/Write register/field by software
• W1C: Write one to clear the state of the field
• RAZWI: Read As Zero Write Ignored register/field by software. This behavior is for reserved register fields.
• Reserved: Reserved field

Table 3 ADDR Register.jpg (39.69 KiB) Viewed 5726 times

Table 3 ADDR Register.jpg (39.69 KiB) Viewed 5726 times

Table 3 ADDR Register

Table 4 DATA Register.jpg (25.28 KiB) Viewed 5726 times

Table 4 DATA Register.jpg (25.28 KiB) Viewed 5726 times

Table 4 DATA Register

Table 5 CTRL Register.jpg (65.82 KiB) Viewed 5726 times

Table 5 CTRL Register.jpg (65.82 KiB) Viewed 5726 times

Table 5 CTRL Register

Table 6 STATUS Register.jpg (66.72 KiB) Viewed 5726 times

Table 6 STATUS Register.jpg (66.72 KiB) Viewed 5726 times

Table 6 STATUS Register